Integrated circuit memory devices used for storing data can typically be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices generally lose any stored data when power supplied to the volatile memory device is interrupted. Nonvolatile memory devices typically retain any stored data even when power supplied to the nonvolatile memory device is interrupted. Accordingly, nonvolatile memory devices have been widely used in, for example, memory cards, mobile telecommunication systems and the like, for their memory retention capabilities.
Integrated circuit memory devices including nonvolatile memory devices typically include cell array regions having a plurality of main cells. The patterns in the cell array regions are generally formed using a photolithography process. Accordingly, main cells located at the edge of the cell array region may be damaged during the photolithography process. The damaged cells may cause non-uniform characteristics of some or all of the main cells in the cell array region.
Recently, manufacturers have begun to include a dummy cell array region surrounding the main cell array region to address the problems caused during the photolithography process discussed above. Referring now to FIG. 1, a cross-sectional view illustrating a portion of a cell array region of conventional NOR-type flash memory devices will be discussed. As illustrated in FIG. 1, the cell array region includes a main cell array region M and a dummy cell array region D adjacent thereto. A p-type well region 3 is provided on an integrated circuit substrate 1. The p-type well region 3 is provided on the cell array region.
A device isolation layer (not shown) is provided at a predetermined region of the p-type well region 3 to define a plurality of parallel active regions. A plurality of parallel gate patterns are disposed to cross over the active regions. The gate patterns may include a plurality of parallel main gate patterns G1 and G2 located in the main cell array region M, and dummy gate patterns G1′ and G2′ located in the dummy cell array region D. Each of the main gate patterns G1 and G2 includes a main word line WL crossing over the active regions, main floating gates FG between the main word line WL and the active regions, a tunnel oxide layer 5 between the main floating gates FG and the active regions, and an inter-gate insulating layer 7 between the main word line WL and the main floating gates FG. The main word lines WL correspond to main control gate electrodes. Similarly, each of the dummy gate patterns G1′ and G2′ includes a dummy word line WL′ crossing over the active regions, dummy floating gates FG′ between the dummy word line WL′ and the active regions, a tunnel oxide layer 5 between the dummy floating gates FG′ and the active regions, and an inter-gate insulating layer 7 between the dummy word line WL′ and the dummy floating gates FG′. The dummy word lines WL′ correspond to dummy control gate electrodes.
A source region S and a drain region D are alternately disposed at the active region between the main gate patterns G1 and G2. Further, the source region S is provided at the active region between the outermost main gate pattern of the main gate patterns G1 and G2 and the dummy gate pattern G2′ adjacent thereto. As a result, a single main cell is formed at every intersection of the main word lines WL and the active regions. An interlayer insulating layer 9 is provided on the integrated circuit substrate having the gate patterns G1′, G2′, G1 and G2 and the source/drain regions S and D. A plurality of parallel bit lines 11 are provided on the interlayer insulating layer 9, and the bit lines 11 cross over the gate patterns G1′, G2′, G1 and G2. Each of the bit lines 11 is electrically coupled to the drain regions D through bit line contact holes (not shown) in the interlayer insulating layer 9.
The erasing operation of the main cells of the conventional NOR-type flash memory device may be achieved by applying a first erasure voltage Ve1 to the main word lines WL, and applying a second erasure voltage Ve2, higher than the first erasure voltage Ve1, to the p-type well region 3 and the dummy word lines WL′. For example, the first erasure voltage Ve1 and the second erasure voltage Ve2 may be negative 9 volts and positive 7 volts, respectively. In this case, the outermost main cells sharing the outermost main gate pattern, for example, the first main gate pattern G1, may not be sufficiently erased due to the parasitic capacitance CFG between the main floating gate FG of the first main gate pattern G1 and the dummy floating gate FG′ of the second dummy gate pattern G2′ adjacent to the first main gate pattern G1. In other words, the voltage induced at the main floating gates FG of the outermost main cells may be higher than the voltage induced at the floating gates FG of the inner main cells surrounded by the outermost main cells due to the presence of the parasitic capacitance CFG.
Referring now to FIG. 2, an equivalent circuit illustrating a coupling ratio of the outermost main cell when the first Ve1 and second Ve2 erasure voltages are applied will be discussed. A first capacitor Ci and a second capacitor Ct are serially connected between the main word line WL (main control gate electrode) of the outermost main cell and the p-type well region 3. The first capacitor Ci corresponds to a parasitic capacitance of the inter-gate insulating layer 7 between the main word line WL and the main floating gate FG and the second capacitor Ct corresponds to a parasitic capacitance of the tunnel oxide layer 5 between the main floating gate FG and the p-type well region 3. Thus, a node VF between the first and second capacitors Ci and Ct corresponds to the main floating gate FG. Further, a third capacitor Cp, which is connected in parallel to the second capacitor Ct, is provided between the main floating gate FG and the P-type well region 3. As illustrated, the third capacitor Cp includes first and second dummy capacitors Ci′ and Ct′ connected in parallel between the dummy floating gate FG′ and the p-type well region 3 and a parasitic capacitance CFG provided between the main floating gate FG and the dummy floating gate FG′ adjacent thereto. The first dummy capacitor Ci′ corresponds to parasitic capacitance of the inter-gate insulating layer 7 between the dummy word line WL′ of the dummy cell adjacent to the outermost main cell and the dummy floating gate FG′, and the second dummy capacitor Ct′ corresponds to a capacitance of the tunnel oxide layer 5 between the dummy floating gate FG′ of the dummy cell and the p-type well region 3.
In the equivalent circuit illustrated in FIG. 2, the floating gate voltage VF induced at the main floating gate FG of the outermost main cell during the erasing operation can be expressed by the following equation:VF={C1×Ve1+(C2+C3)×Ve2}÷(C1+C2+C3)  (Equation 1)where C1 is a capacitance of the first capacitor Ci, C2 is a capacitance of the second capacitor Ct, and C3 is a capacitance of the third capacitor Cp.
As illustrated by Equation 1, if the third capacitance C3 increases, the floating gate voltage VF of the outermost main cell has a high voltage close to the second erasure voltage Ve2 applied to the p-type well region 3. In other words, the electric field applied to the tunnel oxide layer of the outermost main cells during the erasing operation is decreased relative to the electric field applied to the tunnel oxide layer of the inner main cells surrounded by the outermost main cells. This may cause an erase operation to fail in the outermost main cells.
Dummy cells used to improve reliability of a nonvolatile memory device are discussed in Japanese Laid-open Patent No. 59-168992 to Minoru, entitled Nonvolatile Memory and Its Address System.